1. Field of the Invention
The present invention relates to a source driving circuit, display device and method of driving a source driving circuit for a display device.
2. Description of the Related Art
Generally, a display driver integrated circuit (IC) outputs high voltage video data to a display panel. The display driver IC receives digital RGB video data from a timing controller, converts the digital RGB video data into a high-voltage analog signal suitable for the display panel, and outputs the high voltage analog signal to the display panel on a horizontal line basis.
As demand for a high-quality image increases, the number of data bits which represent one pixel gradually increases (e.g., 10 bits). Accordingly, this imposes a time restriction so that more bits of data can be processed during a given cycle allocated for data processing of a corresponding horizontal line.
FIG. 1 is a block diagram of a display device including a conventional source driving circuit. Referring to FIG. 1, the display device includes a plurality of conventional source driving circuits 10-1, 10-2, . . . , 10-i, and a display panel 20. Each of the source driving circuits 10-1, 10-2, . . . , 10-i includes a latch 12, a digital-to-analog converter (DAC) 14, a buffer 16, and an output switch SW.
Digital RGB video data and external control signals are provided from a timing controller (not shown), and internal control signals for controlling the source driving circuits 10 are generated using the external control signals. Each of the source driving circuits 10-1, 10-2, . . . , and 10-i corresponds to a given channel. RGB video data corresponding to each of the channels is input into the latch 12 and converted into an analog signal by the DAC 14. The analog signal is output through the buffer 16 and the output switch SW to the display panel 20.
FIG. 2 is a timing diagram illustrating an operation of the source driving circuit illustrated in FIG. 1. Referring to FIG. 2, in response to a horizontal synchronization signal Hsync that is an input signal of the timing controller, RGB video data ( . . . , N−1, N, N+1, N+2, N+3, . . . ) are sequentially input into the source driving circuits 10-1, 10-2, . . . , 10-i of corresponding channels 1, 2, . . . , i. The input data ( . . . , N−1, N, N+1, N+2, N+3, . . . ) are sequentially or simultaneously converted into analog signals at the source driving circuits 10-1, 10-2, . . . , 10-i, and the analog signals are simultaneously output to the display panel 20 through the output switches SW of the source driving circuits 10-1, 10-2, . . . , 10-i.
Referring to FIG. 2 in an example, data N−1 corresponding to a first horizontal line are sequentially input into the source driving circuits 10-1, 10-2, . . . , 10-i during a period I. The input data N−1 are converted into analog signals by the source driving circuits 10-1, 10-2, . . . , 10-i. The analog signals are simultaneously output to the display panel 20 through the output switches of the source driving circuits 10-1, 10-2, . . . , 10-i during a second period II.
Similarly, the data N corresponding to a second horizontal line are sequentially input into the source driving circuits 10-1, 10-2, . . . , 10-i during the period II. The input data N are converted into analog signals by the source driving circuits 10-1, 10-2, . . . , 10-i, and the analog signals are simultaneously output to the display panel 20 through the output switches of the source driving circuits 10-1, 10-2, . . . , 10-i during a third period III.
Accordingly, and as shown in FIG. 2, the conventional source driving circuits 10 operate with a latency of one horizontal synchronization cycle, and thus have to complete the data processing operation for the simultaneous data output to the display panel 20 within one horizontal synchronization cycle. However, where the data processing operation requires a longer time, the time “t1” shown in FIG. 2 for simultaneously outputting valid data to the display panel 20 is inevitably reduced. This problem becomes more serious when a serial capacitor, instead of a resistor string, is used in the DAC 14 in an effort to achieve a high-gray-scale data processing operation and/or a reduced chip area.